The present invention relates to a waveform reforming circuit for reforming a waveform of an input signal, more particularly relates to a waveform reforming circuit for reforming a signal read from a recording medium etc. with a temporal mean value fluctuating relative with respect to a predetermined value due to an external disturbance component to a binary signal having the predetermined temporal mean value.
The recording medium known as an optical disc is constituted by a transparent plastic substrate having laterally long holes in a circumferential direction referred to as xe2x80x9cpitsxe2x80x9d formed corresponding to the signal, a thin metal film deposited thereon, and a hard resin layer for protecting the thin metal film.
The information recorded on the optical disc is read from the recording medium by focusing light such as a laser beam to the surface of the transparent plastic substrate and converting the light reflected by the thin metal film to an electric signal by an opto-electric conversion element. Namely, at the spot on the circumference of the optical disc on which the light is focused, the intensity of the light reflected from the thin metal film changes between a case where there is a pit and a case where there is no pit, therefore the information recorded based by the pit on the optical disc is converted to a strong or weak electric signal by detecting the intensity of the reflected light by the opto-electric conversion element.
The information recorded on the optical disc by the pit is recorded by a modulation method referred to as eight-to-fourteen modulation (EFM modulation or 8-14 modulation). According to this EFM modulation, what had been an 8-bit code before modulation is converted to a 14-bit code based on an EFM modulation table. The conversion table is selected so that a pulse width of a pulse train resulting from the created code becomes 3T to 11T where one cycle of the pulse is T.
Further, a 3-bit code is added between one 14-bit code and another separately from them. The value of this code is selected for every interval of 14-bit codes so that the probability of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d arising in the created pulse train becomes 50%. Accordingly, the electric signal obtained by reading the information on the optical disc modulated by the EFM modulation method ideally becomes constant in temporal mean value.
In the process referred to as xe2x80x9cmasteringxe2x80x9d for converting an electric signal to pits to prepare a master of an optical disc, light such as a laser beam modulated in accordance with the electric signal is focused on to a photosensitive substance such as a photoresist uniformly coated on for example a polished glass plate, then this is developed to prepare a metal mask forming the master by using the uneven surface of the photoresist formed by the focusing of the light. The pits prepared at this time finely change in shape and size according to various conditions such as the power of the laser used for the mastering and the development time. For example, according to the various conditions, the lengths of the pits change so become slightly longer or shorter by substantially the same amounts even among pits having different lengths.
Such fluctuation of the length of the pits becomes the fluctuation of the pulse width of the electric signal read from the optical disc as it is, therefore the temporal mean value of the electric signal, which ideally should become constant as mentioned above, will fluctuate relative to the ideal value. The phenomenon of the temporal mean value of the read electric signal deviating according to the variance in the lengths of the pits in this way is referred to as xe2x80x9casymmetryxe2x80x9d.
The RF signal directly output from an optical signal reading unit (optical pickup) of the optical disc is not a rectangular wave, but a waveform resembling a sine wave. In order to process this as a digital signal, this sine wave-shaped signal must be converted to a binary pulse signal. However, when the asymmetry of the read signal becomes large, in the process of converting the sine wave-shaped RF signal to a binary pulse signal, the threshold value for the binary coding fluctuates, so erroneous binary coding results and the inconvenience that the error rate of the data is increased occurs.
In order to avoid such an inconvenience, conventionally a waveform reforming circuit as shown in FIG. 1 has been used.
FIG. 1 is a circuit diagram of a conventional waveform reforming circuit for correction of asymmetry.
In FIG. 1, 10 denotes a comparator, 11 a DC bias circuit, 20 a smoothing circuit, 40 a voltage amplifier, R11, R12, R21, R22, and R41 to R43 denote resistors, C11, C21, and C22 denote capacitors, U3 and U4 denote inversion gates, and U40 denotes an operation amplifier. Further, VDD denotes a power supply voltage of the circuit.
The DC bias circuit eliminates the DC component from the RF signal output from the optical pickup, gives a DC bias voltage of a half of the power supply voltage (VDD/2), and outputs the same to the comparator 10.
Specifically, one terminal of the capacitor C11 receives the RP signal output from the optical pickup, while the other terminal of the capacitor C11 is connected to a node of the resistor R11 and the resistor R12 having equal resistance values cascade connected between the power supply voltage and a ground potential. The RF signal is output from this node to the comparator 10.
The comparator 10 compares the RF signal output from the DC bias circuit 10 and the threshold voltage output from the voltage amplifier 40 and outputs an output signal CDATA binary coded to a high level equal to the power supply voltage and a low level equal to the ground potential.
The smoothing circuit 20 receives the output signal CDATA via the cascade connected inversion gates U3 and U4 and outputs the temporal mean value smoothing the output signal CDATA to the voltage amplifier circuit 40.
The voltage amplifier 40 amplifies a difference voltage between the temporal mean value of the output signal CDATA received from the smoothing circuit 20 and the DC bias voltage (VDD/2) and outputs the amplified difference voltage to the comparator 10 as the threshold voltage for the binary coding.
Specifically, a positive side input terminal of the operation amplifier U40 receives the temporal mean value of the output signal CDATA from the smoothing circuit 20, while a negative side input terminal of the operation amplifier U40 is connected to the node of the resistor R41 and the resistor R42 having equal resistance values cascade connected between the power supply voltage and the ground potential. The output voltage of the operation amplifier U40 is fed back via the resistor R43 to the negative side input terminal of the operation amplifier U40 and, at the same time, output to the comparator 10.
Next, an explanation will be made of the operation of the conventional waveform reforming circuit having the above configuration.
The RF signal input from a not illustrated optical pickup circuit to the DC bias circuit 11 is cleared of its DC component by the capacitor C11 and, at the same time, given the DC bias voltage (VDD/2) at the node of the resistor R11 and the resistor R12 and output to the comparator 10.
FIG. 2 is a view of the waveforms of the RF signal in the input and output of the DC bias circuit 11.
In FIG. 2, A denotes the voltage waveform of the RF signal in the input of the DC bias circuit, B denotes the temporal mean value of the voltage waveform A, C denotes the voltage waveform of the RF signal in the output of the DC bias circuit, and D denotes the temporal mean value of the voltage waveform C. Further, the broken lines in the figure represent the temporal mean values in an ideal state free from asymmetry.
As shown in FIG. 2, when a fluctuation of xe2x80x9caxe2x80x9d occurs in the temporal mean value of the input RF signal due to the asymmetry, the ideal value of the temporal mean value of the RF signal in the output of the DC bias circuit 11 causes a fluctuation of xe2x80x9caxe2x80x9d relative to the DC bias voltage (VDD/2). Accordingly, when this RF signal is binary coded with the DC bias voltage (VDD/2) as the threshold value, the margin with respect to the high level signal becomes smaller by exactly xe2x80x9caxe2x80x9d in the example of FIG. 2, therefore the probability of erroneously binary coding the high level signal to a low level becomes high.
In the circuit shown in FIG. 1, by controlling the threshold value when binary coding the RF signal output from the DC bias circuit 11, the increase of the error rate due to failure of the binary coding mentioned above is reduced.
Specifically, the RF signal output from the DC bias circuit 11 is compared with the threshold voltage output by the voltage amplifier 40 at the comparator 10 and is converted to a high level signal and output when the magnitude of the related RF signal is larger than the threshold voltage, while it is converted to a low level signal and output when the magnitude of the related RF signal is smaller than the threshold voltage. In this way, the RF signal is converted to a signal binary coded to the high level and low level.
The output signal of the comparator 10 binary coded to the high level and low level is input to the smoothing circuit 20 via the inversion gates U3 and U4. The inversion gates U3 and U4 are circuits for driving the smoothing circuit 20 with a low output impedance. It is also possible to make the comparator 10 directly drive them.
The binary signal input to the smoothing circuit 20 is smoothed to the DC voltage having the temporal mean value of the binary signal by two low pass type filters comprising the resistor R21 and the capacitor C21, and the resistor R22 and the capacitor C22. In the example of FIG. 1, the smoothing circuit 20 is configured by two low pass type filters constituted by resistors and capacitors, but the smoothing circuit 20 can also be configured by other low pass type filters capable of outputting the temporal mean value of the binary signal output by the comparator 10.
The temporal mean value of the binary signal output by the smoothing circuit 20 is compared with the DC bias voltage (VDD/2) by the voltage amplifier 40, and the difference voltage thereof is amplified and output as the threshold voltage to the comparator 10. Specifically, the temporal mean value of the binary signal obtained by the smoothing circuit 20 is input to the positive side input terminal of the operation amplifier U40. The output voltage of the operation amplifier U40 fluctuates in a direction canceling out the difference voltage between the negative side input terminal and the positive side input terminal of the operation amplifier U40 given the DC bias voltage (VDD/2), whereby the difference voltage between the temporal mean value of the binary signal and the DC bias voltage (VDD/2) is created at the output of the operation amplifier U40 and output to the comparator 10.
For example, when the probability of the high level output increases in the binary signal output by the comparator 10, the magnitude of the temporal mean value obtained by the output of the smoothing circuit 20 becomes larger than the DC bias voltage (VDD/2). By this, the voltage output by the voltage amplifier 40 becomes large. Accordingly, the threshold voltage to be compared with the RF signal at the comparator 10 becomes high, so the probability of the high level output at the comparator is controlled so as to decrease. Conversely, when the probability of the high level output is lowered in the binary signal output by the comparator 10, the magnitude of the temporal mean value obtained by the output of the smoothing circuit 20 becomes smaller than the DC bias voltage (VDD/2). Due to this, the voltage output by the voltage amplifier 40 also becomes small. Accordingly, the threshold voltage to be compared with the RF signal at the comparator 10 becomes low, so the probability of the high level output at the comparator 10 is controlled so as to increase.
In this way, even in a case where asymmetry occurs in the input RF signal, by controlling the threshold value for the binary coding so that the temporal mean value of the output signal becomes constant, the increase of the error rate of the data is prevented.
However, in the conventional waveform reforming circuit shown in FIG. 1, the threshold voltage is created by amplifying the difference between the temporal mean value of the binary signal output by the comparator 10 and the predetermined DC bias voltage (VDD/2) by the voltage amplifier 40, so the asymmetry in accordance with the amplification rate of the difference voltage by the voltage amplifier 40 will remain.
For example, when the temporal mean value of the binary signal output by the comparator 10 has become a voltage lower than the predetermined DC bias voltage (VDD/2) by exactly xe2x80x9caxe2x80x9d, the threshold voltage becomes lower than the predetermined DC bias voltage (VDD/2) by exactly a voltage such as G*a(VDD/2xe2x88x92G*a), if the amplification rate of the difference voltage of the voltage amplifier 40 is defined as G.
Here, when assuming that the RF signal by the output of the DC bias circuit 11 has become lower than the predetermined DC bias voltage (VDD/2) by exactly a voltage such as G*a+a, the RF signal obtained by the output of the DC bias circuit 11 becomes a voltage lower than the threshold voltage by exactly xe2x80x9caxe2x80x9d, therefore it is considered that a difference arises in the probabilities of occurrence of high level and low level voltages in the output of the comparator and that the probability of occurrence of the high level voltage is lowered. When assuming that the temporal mean value of the binary signal obtained by the comparator 10 becomes a voltage lower than the predetermined DC bias voltage (VDD/2) by exactly xe2x80x9caxe2x80x9d due to the reduction of the probability of occurrence of a high level, the system of negative feedback in the waveform reforming circuit shown in FIG. 1 is stabilized in this state. Accordingly, the difference voltage xe2x80x9caxe2x80x9d will remain in the temporal mean value of the binary signal by the comparator 10. This means that the probabilities of occurrence of the high level and low level in the binary signal do not become equal. Namely, there is the problem in that the difference of the data due to the failure of the binary coding is in principle included in the signal output by the above conventional waveform reforming circuit for correcting asymmetry.
Further, when the above relationship is applied to a case where the RF signal obtained by the output of the DC bias circuit 11 has a difference from the predetermined DC bias voltage (VDD/2) of exactly a voltage such as A, it is estimated that the temporal mean value of the binary signal obtained by the comparator 10 has a difference of magnitude proportional to a voltage such as A/(G+1) relative to the predetermined DC bias voltage (VDD/2). Namely, when the asymmetry of input increases, there is the problem in that the asymmetry of the binary signal output by the waveform reforming circuit also increases along with that.
According to the above explanation, if the amplification rate G of the difference voltage of the voltage amplifier is increased, the asymmetry of the binary signal output by the waveform reforming circuit will be lowered in reverse proportion to that. However, the difference caused by the offset voltage etc. of the operation amplifier U40 and the difference due to variation of the resistance values cannot be eliminated even by increasing the amplification rate G. Further, there also exists a problem that the increase of the amplification rate G enlarges the asymmetry by increasing the difference due to such manufacturing variations. Therefore, the amplification rate G can not be enlarged infinitely, so there is a limit in the asymmetry which can be lowered by the conventional circuit shown in FIG. 1.
An object of the present invention is to provide a waveform reforming circuit capable of outputting a binary signal for holding a predetermined temporal mean value in spite of fluctuation of the temporal mean value of an input signal.
To attain the above object, according to the present invention, there is provided a waveform reforming circuit provided with a signal comparison circuit for comparing magnitudes of an input signal and a comparison signal and creating an output signal having a first level when the input signal is larger than the comparison signal and having a second level when the input signal is smaller than the comparison signal, a difference detection circuit for comparing a temporal mean value of the output signal and a predetermined temporal mean value upon receipt of the output signal and outputting a difference signal having a magnitude in accordance with a difference between the temporal mean value of the output signal and the predetermined temporal mean value, and an integration circuit for outputting the comparison signal increasing or decreasing in accordance with a temporal integrated value of the difference signal upon receipt of the difference signal.
Preferably, the difference detection circuit includes a first current source for outputting a current increasing the comparison signal as the difference signal and a second current source for outputting a current decreasing the comparison signal as the difference signal, and the integration circuit includes a capacitor for outputting a charged voltage as the comparison signal to the signal comparison circuit upon receipt of the difference signal obtained by the first current source and the second current source.
Preferably, the first current source includes a first voltage source for outputting a first voltage and a first current controlling means for outputting a current in accordance with the difference between the first voltage and the temporal mean value of the output signal as the difference signal, the second current source includes a second voltage source for outputting a second voltage and a second current controlling means for outputting a current in accordance with the difference between the second voltage and the temporal mean value of the output signal as the difference signal, and the first current controlling means and the second current controlling means output either current as the difference signal in accordance with the level of the output signal.
Preferably, the first voltage source includes a third current controlling means for outputting a current in accordance with the difference between the first voltage and the predetermined temporal mean value and a first current control type voltage source receiving the current output by the third current controlling means and outputting a voltage controlled so that the related current holds a predetermined magnitude as the first voltage, and the second voltage source includes a fourth current controlling means for outputting a current in accordance with the difference between the second voltage and the predetermined temporal mean value and a second current control type voltage source receiving the current output by the fourth current controlling means and outputting a voltage controlled so that the related current holds the predetermined magnitude as the first voltage.
According to the present invention, the input signal input to the signal comparison circuit is compared with the comparison signal by the integration circuit, converted to the output signal having the first level when the input signal is larger than the comparison signal, converted to the output signal having the second level when the input signal is smaller than the comparison signal, and output from the signal comparison circuit.
The difference of the temporal mean value of the output signal input to the difference detection circuit from the predetermined temporal mean value is detected, converted to the difference signal having a magnitude in accordance with the related difference, and output to the integration circuit.
The difference signal input to the integration circuit is integrated in time in the integration circuit, converted to the comparison signal increasing or decreasing in accordance with the integrated value, and output to the signal comparison circuit.
According to the present invention, the difference signal is output from the first current source to the integration circuit as the current increasing the comparison signal and, at the same time, output from the second current source to the integration circuit as the current decreasing the comparison signal.
The integration circuit has the capacitor, charged or discharged by the currents by the first current source and the second current source, and outputs the charged voltage as the comparison signal to the signal comparison circuit.
According to the present invention, the difference of the temporal mean value of the output signal from the first voltage is detected at the first current controlling means, converted to the difference signal as the current having a magnitude in accordance with the related difference, and output to the capacitor. Further, the difference of the temporal mean value of the output signal from the second voltage is detected at the second current controlling means, converted to the difference signal as the current having a magnitude in accordance with the related difference, and output to the capacitor.
The current in accordance with the difference between the first voltage and the predetermined temporal mean value is output from the third current controlling means to the first current control type voltage source. The first current control type voltage source receiving the related current outputs the first voltage controlled so that the related current becomes a predetermined current.
Further, the current in accordance with the difference between the second voltage and the predetermined temporal mean value is output from the fourth current controlling means to the second current control type voltage source, and the second current control type voltage source receiving the related current outputs the second voltage controlled so that the related current becomes the predetermined current.